Samsung Details Next-Gen Exynos 5 Dual Processor

August 10, 2012

Samsung has unveiled details about its upcoming ARM Dual Cortex-A15 based mobile application processor, otherwise known as the Exynos 5 Dual. The 32nm dual-core 1.7GHz CPU is considered an upgrade over the current Exynos 4 Quad found in the international version of the Samsung Galaxy S III and should be competitive with Qualcomm’s 28nm Snapdragon S4 chipset. Its quad-core Mali-T604 GPU supports display resolutions of up to 2560×1600 (WQXGA) and stereoscopic 3D. The Exynos 5 Dual also provides 12.8 GB/s memory bandwidth with 2-port 800MHz LPDDR3 for heavy traffic operations, as well as SATA, UART, USB3.0, and eMMC4.5 interfaces for crisp transmissions. Overall, users can expect significant improvements in performance and battery life over its predecessor. Devices with the Exynos 5 Dual have not been announced yet.


World’s first Low-Power Dual Core Cortex-A15 Processor with 1.7 GHz Clock speed
- ARM Cortex-A15 Dual Core processor with the clock speed up to 1.7 GHz (14,000 DMIPS)
- High Memory Bandwidth with WQXGA resolution required for graphic-intensive applications (12.8 GB/s)
- Diverse Memory Support: Supports LPDDR3/LPDDR2/DDR3 Dual channel memory

Top-Notch 3D Performance: Supports WQXGA Resolution
- World’s best mobile 3D graphic processor: Supports WQXGA 60 fps 3D graphics
- 32 nm HKMG process and advanced architecure enhances the performance

Low Power Consumption (30% lower than 45nm)
- 32 nm HKMG process decreases the power consumption drastically
- Manages power with Multiple Power Domain and Dynamic Voltage Frequency Scalling
- Low-power display scheme: This includes embedded DisplayPort and panel self-refresh technology
- System-level power optimization with companion PMIC (S5M8767)

High-Performance Hardware MFC and ISP
- Experience full-profile support of 1080P 60 fps Multi Format Codec
- Experience high-quality camera with 8Mpixel 30 fps Embedded Image Signal Processor

- CortexA15 dual core subsystem with 64-/128-bit SIMD NEON
- 32KB (Instruction)/32KB (Data) L1 Cache and 1MB L2 Cache
- 128-bit Multi-layered bus architecture
- Internal ROM and RAM for secure booting, security, and general purposes
- Memory Subsystem
* 2-ports 32-bit 800MHz LPDDR3/DDR3 Interfaces
* 2-ports 32-bit 533MHz LPDDR2 Interfaces
- 8-bit ITU 601 Camera Interface
- Multi-format Video Hardware Codec: 1080p 60fps (capable of decoding and encoding MPEG-4/H.263/H.264 and decoding only MPEG-2/VC1/VP8)
- 3D and 2D graphics hardware, supporting OpenGL ES 1.1/2.0/Halti, OpenVG 1.1 and OpenCL 1.1 full profile
- Image Signal Processor : supporting BayerRGB up to 14bit input with 14.6MP 15fps, 8MP 30fps through MIPI CSI2 & YUV 8bit interfaces and special functionalities such as 3-dimensional noise reduction (3DNR), video digital image stabilization (VDIS) and optical distortion compensation (ODC)
- JPEG Hardware Codec
- LCD single display, supporting max WQXGA, 24bpp RGB, YUV formats through MIPI DSI or eDP
- Simultaneously display of WQXGA single LCD display and 1080p HDMI
- HDMI 1.4 interfaces with on-chip PHY
- 2-ports (4-lanes) MIPI CSI2 interfaces
- 1-port (4-lanes) eDisplayPort (eDP)
- 1-channel USB 3.0 Device or Host, supporting SS (5Gbps) with on-chip PHY
- 1-channel USB 2.0 Host or Device, supporting LS/FS/HS (1.5Mbps/12Mbps/480Mbps) with on-chip PHY
- 2-channel USB HSIC, supporting 480Mbps with on-chip PHY
- 1-channel HS-MMC 4.5
- 1-channel SDIO 3.0
- 2-channel SD 2.0 or HS-MMC4.41
- 4-channel high-speed UART (up to 3Mbps data rate for Bluetooth 2.1 EDR and IrDA 1.0 SIR)
- 3-channel SPI
- 1-channel AC-97, 2-channel PCM, and 3-channel 24-bit I2S audio interface, supporting 5.1 channel audio
- 1-channel S/PDIF interface support for digital audio
- 4-channel I2C interface support (up to 400kbps) for PMIC, HDMI, and general-purpose multi-master
- 4-channel HS-I2C (up to 3.1 Mbps)
- Samsung Reconfiguration Processor supports low power audio play
- MIPI-HSI v1.1, supporting 200Mbps full-duplex
- C2C, supporting through path between DRAM and MODEM
- Security subsystem supporting hardware crypto accelerators, ARM TrustZone and TZASC
- 32-channel DMA Controller
- Configurable GPIOs
- Real time clock, PLLs, timer with PWM, multi-core timer, and watchdog timer

Source: Samsung, ARM via theVerge

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